HW 3 SOlution

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  • (5 points) Write a Verilog program that implements the Moore FSM shown below.

 

  • (5 points) Write a testbench that tests your FSM module for the input sequence r = 0 0 1 0 1 1 1 1 0

 

  • (2 point bonus) This is an optional problem. Simulate your FSM using the testbench from question 2. Turn in a hard copy of the timing diagram.

                                                0                 1

 

A/O                      0                 B/O                                         C/1

 

 

                   1                                              1

 

D/0                                          E/1

 

 

 

 


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