- Consider the following code:
if(A < 10)
Y = 0;
else if (A > 10 & A <= 15)
Y = 1;
Assume A can assume a value between -2 and +22.Why would a synthesizer believe a latch is necessary? Simply saying there is no “else” clause is not the answer. That causes a latch to be inferred but doesn’t explain why the synthesizer puts one in the design. I want to know why a latch is necessary.
- What are three ways of preventing latch inference in case statements?
- Why should module outputs be registered?
- Consider the following module:
module U1(in1, in2, y ,clk);
input in1, in2, clk;
always @(posedge clk)
s = in1 ^ in2;
assign y = ~s;
Edit the code so the module has a registered output.
- Consider the following Verilog code:
y = 1;
y = 2;
y = 3;
y = 4;
y = 0;
- Show what would most likely be synthesized.
- Rewrite the code from the previous problem as a case statement. Show what would be synthesized if the parallel_case synthesis directive is used.