Description
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1. |
Design a digital circuit that detects which of the two 5-bit input numbers |
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(InA and InB) is larger. The circuit will output a two bit signal called Out |
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such that: |
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Situation |
Out |
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InA = InB = 0 |
00 |
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InA > InB |
01 |
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InA < InB |
10 |
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InA = InB ≠ 0 |
11 |
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Use structural Verilog and Quartus. |
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2. |
Write a Verilog testbench for your circuit and simulate by ModelSim to see |
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the correctness of your design. |
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3. |
Upload your design to DE0 FPGA board and verify it on the board. |
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4. |
Bonus (15pts): If you design without using any addition or subtraction |
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process |
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Rules:
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All project details (even the schematic) will be announced at next PS (October 17). So attend the PS for your own good!
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Behavioral Verilog is not permitted. Thus, first draw your schematic on a paper.
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Designs that are not even simulating can at most get 20pts.
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You should show your simulation and board execution during demo hour and be graded accordingly. Demo hour will be announced on Moodle.
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No late submissions even if 1 minute.
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The input-output names must be exactly the same as given above.
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Honor code: It is not a group project. Any cheating means at least -100 for both sides. Do not share your codes and design to any one in any circumstance. Be honest and uncorrupt not to win but because it is right!