Project 3 Phase Solution

$35.00 $30.80

Description

  • Phase 1: In-lab Exercises

 

1.1 Instructions

 

  1. You are expected to work in groups of 4 at each table. All brainstorming discussions must be done as a team to promote collaborative thinking.

 

  • If you happen to be at a table with fewer than 4 people, you can choose to work with fewer people or let your TA’s know to assist you in nding extra partner(s).

 

  1. Download the collateral from Slack and use the skeletal les provided. Do not change the name of the les nor the names of the pins.

 

  1. Add your full name and UIN to the introductory comment present in each .hdl  le.

 

  1. Complete the problem set provided in this document on your own sheet of paper. Make sure your drawings are clear and handwriting is legible. Show your work.

 

  1. Implement the .hdl le for each chip. Keep these handy because you will use some of them and turn them in for Project 3 Phase 2.

 

  1. The .tst and .cmp les are optional for today’s assignment, but we recommend verifying the behavior of your chip as it will be graded based on correctness.

 

1.2 Submission

 

  1. Submissions must be done individually. Even though you are nding the solutions as a team, each of you is supposed to do the implementation individually, so we know you got the concepts.

 

  1. Including your name and UIN, turn in your sheet of paper with the solutions to the problem set by the end of the lab session.

 

  1. In a zipped folder named LastName FirstName UIN Lab3.zip turn in the .hdl les before midnight tonight on eCampus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1.3 Problem Set (30 Points)

 

  1. (1 point) A Data Flip Flop (DFF) is characterized with one 1-bit data input in, one 1-bit data output out, and one 1-bit clock input clk. At clock cycle t, what is the output out(t)?

 

 

 

 

 

 

 

 

  1. (7 points) A Bit is characterized with one 1-bit data input in, one 1-bit control signal load, one 1-bit clock signal clk, and one 1-bit output out.

 

  • (1 point) Draw the interface block diagram (inputs and outputs) of a Bit.

 

 

 

 

 

 

 

Bit

 

 

 

 

 

 

  • (1 point) Finish the conditional statements below describing the behavior of a Bit.

 

 

If load(t) then: else

 

  • (2 points) Draw the logic gate diagram for a Bit using a DFF.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(d) (3 points) Implement the .hdl le for the Bit chip.

 

 

 

 

 

 

 

 

 

 

 

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  1. (9 points) An n-bit Register is characterized with one n-bit data input in, one 1-bit control signal load, one 1-bit clock signal clk, and one n-bit data output out.

 

  • (1 point) Draw the interface block diagram (inputs and outputs) of the multi-bit Register. Make sure you indicate the number of bits going through wires with more than 1 bit.

 

 

 

 

 

 

n-bit Register

 

 

 

 

 

 

  • (3 points) Draw a the logic gate diagram to implement a 4-bit register with one 4-bit input in, one 4-bit output out, one 1-bit control signal load, and one 1-bit clock signal clk.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c) (5 points) Implement the .hdl le for the 16-bit Register provided.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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  1. (13 points) A 16-bit RAM8 is characterized by one 16-bit data input in, one 3-bit control input address, one 1-bit control signal load, one 1-bit clock signal clk, and one 16-bit data output out.

 

  • (2 points) Draw the interface block diagram (inputs and outputs) of the 16-bit RAM8. Make sure you indicate the number of bits going through wires with more than 1 bit.

 

 

 

 

 

 

 

 

 

RAM8

 

 

 

 

 

 

 

 

  • (3 points) Draw the inner logic block diagram of the 16-bit RAM8. load

 

 

 

 

 

 

16

 

in[15:0]

 

16

 

out[15:0]

 

3

 

addr[15:0]

 

 

 

 

 

 

 

 

 

 

clk

 

(c) (8 points) Implement the .hdl le for the 16-bit RAM8 le provided.

 

 

 

 

 

 

 

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