# Project 2 Phase 1: Solution

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## Description

• Phase 1: In-lab Exercises

1.1 Instructions

1. You are expected to work in groups of 4 at each table. All brainstorming discussions must be done as a team to promote collaborative thinking.

• If you happen to be at a table with fewer than 4 people, you can choose to work with fewer people or let your TA’s know to assist you in nding extra partner(s).

1. Download the collateral from Slack and use the skeletal les provided. Do not change the name of the les.

1. Add your full name and UIN to the introductory comment present in each .hdl  le.

1. Complete the problem set provided in this document on your own sheet of paper. Make sure your drawings are clear and handwriting is legible. Show your work.

1. Implement the .hdl, .tst, and .cmp le for each chip. Keep these handy because you will use them and turn them in for Project 2 Phase 2.

1.2 Submission

1. Submissions must be done individually. Even though you are nding the solutions as a team, each of you is supposed to do the implementation individually, so we know you got the concepts.

1. Including your name and UIN, turn in your sheet of paper with the solutions to the problem set by the end of the lab session. Include your name and UIN.

1. In a zipped folder named LastName FirstName UIN Lab2.zip turn in the .hdl, .tst, and .cmp les before midnight on eCampus.

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1.3 Problem Set (30 Points)

1. (6 points) A Half Adder is characterized with two 1-bit data inputs a and b, a 1-bit data output sum, and a 1-bit carry output carry.

• (1=2point) Draw the interface block diagram (inputs and outputs) of the Half Adder.

(b) (1=2 point) Complete the truth table for the Half Adder.

 Inputs Outputs a b carry sum 0 0 0 1 1 0 1 1

• (1 point) Write the logic expressions for outputs carry and sum from the truth table above, then minimize them using Boolean Algebra.

• (1 point) Draw logic gate diagrams to implement the minimized logic expressions for carry and sum.

(e) (3 points) Implement the .hdl, .tst, and .cmp les for the Half Adder chip.

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1. (10 points) A Full Adder is characterized with two 1-bit data inputs a and b, a 1-bit carry input c, a 1-bit data output sum, and a 1-bit carry output carry.

• (1=2point) Draw the interface block diagram (inputs and outputs) of the Full Adder.

(b) (11=2 points) Complete the truth table for the Full Adder.

 Inputs Outputs a b c carry sum 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

• (2 points) Write the logic expressions for outputs carry and sum from the truth table above, then minimize them using Boolean Algebra.

• (2 points) Draw logic gate diagrams to implement the minimized logic expressions for carry and sum.

(e) (4 points) Implement the .hdl, .tst, and .cmp les for the Full Adder chip.

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1. (12 points) A 4-bit ripple carry adder Add4 is characterized by two 4-bit data inputs a[3 : 0] and b[3 : 0],

a 4-bit data output sum[3 : 0], and a 1-bit carry output carry.

• (4 points) Draw the inner logic block diagram of Add4 using one Half Adder and three Full Adders.

a[3:0] b[3:0]

 4 4

4

carry sum

(b) (4 points) Draw the inner logic block diagram of Add4 using full adders only.

a[3:0] b[3:0]

 4 4

4

carry sum

(c) (4 points) Implement the .hdl, .tst, and .cmp les for the Add4 chip using full adders only.

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