Lab Assignment 1 Solved

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Description

Objective

This lab is aimed at getting you familiar with using the ModelSim simulator.

Instructions

Write a VHDL program consisting of a single entity whose architecture is a single process that implements the following logic gate with 3 inputs and 1 output

inputs |output

———————————–

a_in b_in c_in | result

———————————–

0

0

0

| 0

0

1

0

| 1

1

0

0

| 1

1

1

0

| 0

0

0

1

| 1

0

1

1

| 0

1

0

1

| 0

1

1

1

| 1

Use exactly the names given above for the signals. All your signals should be of type bit (NOT integer).

Deliverables

Please turn in the following things for this lab:

  1. A printout of your VHDL code.

  1. A screen shot of your exhaustive simulation.

  1. A screen shot of a successful compilation of your code.